1. Technical Field
The present invention relates to a liquid crystal display device for displaying an image based on a received video signal, and relates in particular to a liquid crystal display device provided with an improved driver interface for a liquid crystal display panel.
2. Prior Art
Generally, when displaying an image on a liquid crystal display panel, first, an image signal from the graphics controller of a system, including a PC, or of a system unit is output via a video interface. Then, upon receiving the image signal, an LCD (liquid crystal display) controller LSI transmits a signal to each of the individual ICs in a source driver (an X driver or an LCD driver) and a gate driver (a Y driver), and applies a voltage to each source electrode and each gate electrode in a TFT array, arranged as a matrix, until finally, an image is displayed.
An interface used by a conventional LCD driver is shown in FIG. 20. In FIG. 20, one constituent of a source driver is an IC chip 301, fewer than twenty of which are provided for one LCD panel. As is commonly done with the chip on glass (COG) technique, the chips 301 are mounted on a glass substrate, which constitutes the LCD panel, outside an area covered by a color filter. Each of the chips 301 is then connected to a power feed line (Power) 302, and each of them receives a video interface signal 303 and a sampling start signal (StartPulse) 304. In consonance with a gray scale of 8 bits, provided for the video interface signal 303 and the sampling start signal 304 are a total of 28 lines, 27 of which are used for the video interface signal 303 to carry 24 bits of RGB video data, comprising one 8 bit set for each of the three colors R, G and B, a strobe signal for outputting received RGB data to the LCD, a polarity signal for designating the polarity of a voltage that is to be applied to the LCD, and a clock signal for transmitting a dot clock of about 65 MHz when an XGA (1024×768 dots) panel is employed. The sampling start signal 304 is used to initiate the sampling of the RGB video data.
As is shown in FIG. 20, a cascade-connection may be used for the sampling start signal 304. However, the power line 302 and the 27 lines of the video interface signal 303 are arranged on an adjacently and separately provided printed circuit board (PCB) or flexible printed circuit board (FPC). That is, since it is difficult for the conventional technique to provide the wiring between the chips on the glass substrate, a line wiring section is formed on the adjacent printed circuit board so that video data can be transmitted through a bus that connects the chips. In this case, no problem has arisen considering the number of video signals input to the LCD source driver.
Recently, in order to further reduce manufacturing costs, attention has been focused on a COG&WOA (Wiring On Array) technique. In addition, another technique has been developed whereby a driver LSI is arranged on a TCP (Tape Carrier Package) so that the LSI is connected, via the TCP, to a TFT array substrate (a glass substrate). If, using these techniques, the IC can be attached to the glass substrate directly, or via the TCP, and the wiring formed on the printed circuit board can be eliminated, the manufacturing costs can be greatly reduced.
However, with a conventional bus connection, a great number of video signals are input to the LCD source driver, and implementation of a COG&WOA LCD module can not be performed. That is, if multiple lines, such as 28 lines, are to be moved unchanged to the glass substrate, a frame space of 1 to 2 cm is required around a liquid crystal cell. If such a large frame space is provided, this will constitute the provision of a condition that runs counter to current demand, which is for a reduced frame size, and accordingly, the value of the product will be reduced.
As a technique for reducing the frame size by using a COG structure, a wiring arrangement whereby an FPC is so constructed that it covers the chips, and the chips are connected to the FPC is proposed in Japanese Unexamined Patent Publication No. Hei 5-107551. According to this technique, the frame size can be reduced, but the thickness of the panel can not. Further, since in this structure all the chips are connected directly to the FPC, the number of connection terminals is increased, and the reliability of the connections will not be satisfactory. In addition, since multiple FPC connection terminals are provided between the chips, large gaps are required between the chips, and this makes it difficult to reduce the size of the device.
To resolve the above described shortcomings, it is one object of the present invention to drastically reduce the number of video signals that are input to an LCD driver and to reduce the manufacturing costs by implementing the COG&WOA technique.
It is another object of the present invention to provide a structure that can constitute a fast, compact serial interface for low power consumption, and that can minimize the number of fast operating circuits that are used, thereby suppressing an increase in power consumption and an increase in chip size.